To make it easier the file should be called either makefile or
Makefile. This particular example can be found
here. Remember, the indented "rules"
under the target need to be indented with tabs. With a file like this then
you only need to type make to get it to build the default target
(all -> hw3 in this case). To go to any other target just use the name
of the target as in make clean to execute the clean target. More
documentation on make and makefiles can be found
here.
# variable definitions
#
CC = cc
CFLAGS = -Wall -pedantic
LIBS = -lm
# first target is the default target of the make command
#
all: hw3
# target for building hw3
# $@ is a built in variable that tells it to substitute the target name
# $^ is a built in variable that tells it to substitute the dependencies
#
hw3: lib.o main.o
${CC} -o $@ $^ ${LIBS}
# dependencies for the objects
# this uses the implicit rule below to build a .o from a .c
#
lib.o: lib.c header.h
main.o: main.c header.h
# target to clean up extra files
#
clean:
${RM} hw3 *.o
# generic (usually built in) target to compile a .c file to a .o file with
# the same name ($< is a built in variable telling it to substitute the name
# of the file in there)
#
.c.o:
${CC} ${CFLAGS} -c $<
fix_perms:
